American Megatrends, Inc. (AMI)

The POST checkpoints performed in AMIBIOS were revised and updated in 1995 and have not undergone significant changes to date. The first description of POST codes or, as AMI calls them, “check points” in their current form appeared in connection with the release of the V6.24 kernel, 07/15/95. Some changes have been made to AMIBIOS V7.0, which are reflected in this document.

Features of performing AMIBIOS startup procedures

If during the startup process the data 55h, AAh appears in the diagnostic port, you should not compare this information with POST codes - we are dealing with a typical test sequence, the task of which is to check the integrity of the data bus.

At the start stage, the output to the diagnostic port of data is specific to each platform. In some implementations, the first code rendered is associated with actions, which AMI calls chipset specific stuff. This procedure is accompanied by outputting the CCh value to port 80h and performing a number of actions to configure the system logic registers. As a rule, the CCh code occurs in cases where system logic from Intel is used, built on the basis of a controller

PIIX are TX, LX, BX chipsets.

Some on-board I/O chips contain an RTC and keyboard controller, which are disabled at startup. The purpose of the BIOS is to initialize these board resources for further use. In this case, the first startup procedure associated with setting up the keyboard controller is accompanied by the output of the value 10h, then the RTC is initialized, as evidenced by the appearance of the DDh code in the diagnostic port. It should be noted that the failure of at least one of these resources will result in the system board as a whole not starting at the very first stage of POST execution.

On a number of boards, the initialization process begins with the CPU switching to protected mode. In this case, following the first rendered code 43h, the POST execution continues as described in the AMIBIOS documentation - control is transferred to point D0h.

Unpacked initialization procedure codes

(Uncompressed Init Code Check Points)

E.E.In modern AMIBIOS implementations, the first code rendered is associated with accessing the device from which it is possible to boot to restore the BIOS

CCInitializing system logic registers

CDFlash ROM type not recognized

C.E.Checksum mismatch in the startup BIOS

CFError in accessing spare Flash ROM chip

DDEarly initialization of the RTC, which is integrated into the SIO chip

D0Disable non-maskable NMI interrupt. Working out a time delay for attenuation of transient processes. Checking Boot Block checksum, stopping if there is a mismatch

D1Perform memory regeneration procedure and Basic Assurance Test. Switching to 4 GB memory addressing mode

D3Determination of capacity and primary memory test

D4Return to real memory addressing mode. Early initialization of the chip set Installation of the stack

D5Transferring the POST module from Flash ROM to the transit memory area

D6If the checksum does not match or CTRL+Home, a transition to the Flash ROM recovery procedure is performed (Code E0)

D7Transferring control to a utility program that unpacks the system BIOS

D8Complete unpacking of the system BIOS

D9Transferring system BIOS control to Shadow RAM

D.A.Reading information from SPD (Serial Presence Detect) DIMMs

D.B.Setting the MTRR of the CPU registers

DCThe memory controller is programmed according to data received from the SPD

DESystem memory configuration error. Fatal error

DFSystem memory configuration error. Sound signal

10 Early initialization of the keyboard controller

11 Return from STR (Suspend to RAM) state

12 Restoring access to SMRAM (System Management RAM)

13 Memory regeneration restoration

14 Search and initialize VGA BIOS Flash ROM rewrite procedure codes (Boot Block Recovery Codes)

E0Preparations are being made to intercept INT19 and the ability to start the system in simplified mode is checked.

E1Setting interrupt vectors

E3Recovering CMOS contents, searching and initializing BIOS

E2Preparing interrupt controllers and direct memory access

E6Enable system timer and FDC interrupts

E.C.Reinitializing IRQ and DMA controllers

EDInitializing the drive

E.E.Reading the boot sector from a floppy disk

E.F.Disk Operation Error

F0Finding the AMIBOOT.ROM file

F1The file AMIBOOT.ROM was not found in the root directory

F2 Read FAT

F3Reading AMIBOOT.ROM

F4The size of the AMIBOOT.ROM file does not match the size of the Flash ROM

F5 Disabling Internal Cache

FBFlash ROM Type Definition

F.C.Erasing the main Flash ROM block

FDProgramming the main Flash ROM block

FFBIOS restart Codes of the unpacked system BIOS, executed in ShadowRAM

(Runtime code is uncompressed in F000 shadow RAM)

03 Disable non-maskable NMI interrupt. Reset Type Definition

05 Stack initialization. Disable memory and USB controller caching

06 Executing a utility program in RAM

07 Processor recognition and APIC initialization

08 Checking the CMOS checksum

09 Checking the operation of the End/Ins keys

0ABattery failure check

0BClearing the keyboard controller buffer registers

0CA test command is sent to the keyboard controller

0EFinding additional devices supported by the keyboard controller

0FInitializing the keyboard

10 A reset command is sent to the keyboard

11 If the End or Ins key is pressed, the CMOS is reset

12 Placing DMA controllers in a passive state

13 Chipset initialization and L2 cache

14 Checking the system timer

19 DRAM regeneration request generation test is running

1AChecking the duration of the regeneration cycle

20 Initializing Output Devices

23 The keyboard controller input port is read. Questioned Keylock Switch and Manufacture Test Switch

24 Preparing to initialize the interrupt vector table

25 Interrupt vector initialization complete

26 The status of the Turbo Switch jumper is polled through the keyboard controller input port

27 Primary initialization of the USB controller. Updating the microcode of the starting processor

28 Preparing to install video mode

29 Initializing the LCD panel

2ASearch for devices supported by additional ROMs

2BInitializing VGA BIOS, checking its checksum

2CExecuting VGA BIOS

2DMatching INT 10h and INT 42h

2ESearch for CGA video adapters

2FCGA adapter video memory test

30 Test of CGA adapter scan generation circuits

31 Error in video memory or scanning circuits. Finding an alternative CGA video adapter

32 Test of video memory of an alternative CGA video adapter and scan circuits

33 Poll the status of the Mono/Color jumper

34 Setting text mode 80x25

37 Video mode is set. Screen cleared

38 Initialization of on-board devices

39 Displaying error messages from the previous step

3ADisplaying the “Hit DEL” message to enter CMOS Setup

3BStart preparing for a memory test in protected mode

40 Preparing GDT and IDT descriptor tables

42 Switching to protected mode

43 The processor is in protected mode. Interrupts enabled

44 Preparing to test the A20 line

45 A20 line test

46 RAM size determination completed

47 Test data recorded in Conventional Memory

48 Rechecking Conventional Memory

49 Extended Memory Test

4BMemory reset

4CIndication of the zeroing process

4DRecording the resulting Conventional and Extended memory sizes into CMOS

4EIndication of the actual amount of system memory

4FExtended Conventional Memory test running

50 Conventional Memory size correction

51 Extended Memory test

52 Conventional Memory and Extended Memory volumes saved

53 Delayed parity error handling

54 Disable parity and non-maskable interrupt processing

57 Initializing the memory region for POST Memory Manager

58 You are prompted to enter CMOS Setup

59 Returning the processor to real mode

60 Checking page DMA registers

62 Test of address registers and forwarding length of DMA#1 controller

63 Test of address registers and forwarding length of DMA#2 controller

65 Programming DMA controllers

66 Clearing the Write Request and Mask Set POST registers

67 Programming Interrupt Controllers

7FResolving NMI request from additional sources

80 Sets the interrupt servicing mode from the PS/2 port

81 Keyboard interface test for reset errors

82 Setting the keyboard controller operating mode

83 Checking Keylock Status

84 Memory capacity verification

85 Displaying Error Messages

86 Configuring the system for Setup operation

87 Unpacking the CMOS Setup program into Conventional Memory.

88 Setup program completed by user

89 Completed state recovery after Setup operation

8BReserving memory for an additional BIOS variable block

8CProgramming Configuration Registers

8DPrimary initialization of HDD and FDD controllers

8FReinitializing the FDD Controller

91 Configuring the HDD Controller

95 Performing a ROM Scan to look for additional BIOSes

96 Additional configuration of system resources

97 Verifying the signature and checksum of the optional BIOS

98 Setting up System Management RAM

99 Setting the timer counter and parallel port variables

9AGenerating a list of serial ports

9BPreparing an area in memory for a coprocessor test

9CInitializing the coprocessor

9DCoprocessor information is stored in CMOS RAM

9EKeyboard Type Identification

9FSearch for additional input devices

A0 Formation of registers MTRR (Memory Type Range Registers)

A2Error messages from previous initialization steps

A3Setting the keyboard auto-repeat timing

A4Defragmenting unused RAM regions

A5Setting the video mode

A6 Cleaning the screen

A7Transferring BIOS executable code to Shadow RAM area

A8Initializing additional BIOS in segment E000h

A9Returning control to the system BIOS

A.A.USB bus initialization

ABPreparing the INT13 module to serve disk services

A.C.Building AIOPIC tables to support multiprocessor systems

ADPreparing the INT10 module for servicing video services

A.E.DMI initialization

B0System Configuration Table Displayed

Features of the Device Initialization Manager

In addition to the above POST codes, messages about events during the execution of Device Initialization Manager (DIM) are output to the diagnostic port. There are several checkpoints that indicate the initialization status of system or local buses.

2AInitializing devices on the system bus

39 Indication of errors that occur during bus initialization

95 Initializing buses controlled by additional BIOS DE System memory configuration error

DFSystem memory configuration error

The information is displayed in word format, the low byte of which coincides with the system POST code, and the high byte indicates the type of initialization procedure being performed. The most significant tetrad in the high byte indicates the type of procedure being executed, and the low tetrad determines the bus topology for its application.

Senior tetrad:

0 initialization of all devices on all buses is prohibited

1 initialization of static devices

2 initialization of output devices

3 initialization of input devices

4 initializing system boot devices (IPL)

5 initialization of general purpose devices

6 error message

7 initialization of devices controlled by additional ROMs

Junior tetrad:

0 system initialization procedures (DIM)

1 on-board device connection buses

2 ISA Legacy bus

3 EISA bus

4 ISA PnP bus

5 PCI bus

6 PCMCIA bus

7 MCA bus

If a system memory configuration error is detected, the DE code, DF code, and configuration error code are output to port 80h sequentially in an endless loop, which can take the following values:

00 RAM not detected

01 Various types of DIMMs installed (example, EDO and SDRAM)

02 Reading SPD content failed

03 The module does not meet the requirements for operation at the specified frequency

04 The module cannot be used on this system

05 The information in the SPD does not allow the installed modules to be used

06 Low memory page error detected

This table contains POST codes that are displayed during the full POST procedure.

CF Detects processor type and tests CMOS read/write
C0 The chipset and L1-, L2-cache are pre-initialized and programmed
interrupt controller, DMA, timer
C1 The type and amount of RAM is detected
C3 BIOS code is unpacked into a temporary area of ​​RAM
0C BIOS checksums are checked
C5 BIOS code is copied to shadow memory and control is transferred to the Boot Block module
01 XGROUP module is unpacked at physical address 1000:0000h
02 Processor initialization. The CR and MSR registers are set
03 I/O resources are determined (Super I/O)
05 Clears screen and CMOS status flag
06 Coprocessor is being checked
07 Keyboard controller is identified and tested
08 Keyboard interface is detected
09 Initializing the Serial ATA controller
OA Detects the keyboard and mouse that are connected to the PS/2 ports
0B AC97 audio controller resources are being installed
OE Testing memory segment F000h
10 The type of flash memory is determined
12 CMOS tested
14 Sets values ​​for chipset registers
16 The clock generator is initially initialized
18 The processor type, its parameters and L1 and L2 cache sizes are determined
1B The interrupt vector table is initialized
1C Checks CMOS checksums and battery voltage
1D Power management system is defined
1F Loads the keyboard matrix (for laptops)
21 The Hardware Power Management system is initializing (for laptops)
23 Math coprocessor, disk drive, chipset initialization are tested
24 The processor microcode is being updated. A resource distribution map is created
Plug and Play devices
25 Initial PCI initialization: devices are listed, adapter search
VGA, VGA BIOS entry at C000:0
26 The clock frequency is set according to CMOS Setup. Synchronization is disabled
unused DIMM and PCI slots. The monitoring system is initialized
(H/W Monitor)
27 Interrupt INT 09h enabled. The keyboard controller is initialized again
29 MTRR registers are programmed, APIC is initialized. Controller is being programmed
IDE. The processor frequency is measured. The video system BIOS extension is called
2B Search for video adapter BIOS
2D The Award splash screen is displayed, information about the processor type and its speed
33 Keyboard reset
35 First DMA channel being tested
37 Second DMA channel being tested
39 DMA page registers are tested
3C Configuring 8254 controller (timer)
3E Checking the 8259 interrupt controller
43 Interrupt controller is checked
47 ISA/EISA buses are tested
49 The amount of RAM is calculated. Registers are configured for the processor
AMD K5
4E MTRR registers are programmed for Syrix processors. L2 cache is initialized
and APIC
50 USB bus detected
52 The RAM is tested and the results are displayed. Clearing extended memory
53 If the CMOS is cleared, the login password is reset
55 Displays the number of processors (for multiprocessor platforms)
57 The EPA logo is displayed. Initial Initialization of ISA PnP Devices
59 Virus protection system is determined
5B Prompt for running BIOS update from floppy disk
5D Launches Super I/O controller and integrated audio controller
60 Entering CMOS Setup if the Delete key was pressed
65 PS/2 mouse is initializing
69 L2 cache enabled
6B Chipset registers are configured according to BIOS Setup
6D Assigns resources for ISA PnP devices and COM ports for integrated
devices
6F Initializes and configures the floppy disk controller
75 IDE devices are detected and installed: hard drives,
CD/DVD, LS-120, ZIP, etc.
76 Information about detected IDE devices is displayed
77 Serial and parallel ports are initialized
7A The math coprocessor is reset and ready for operation.
7C Defines protection against unauthorized writing to hard drives
7F If there are errors, a message is displayed and the Delete and F1 keys are pressed
82 Memory is allocated for power management and changes are written to the ESCD table.
The splash screen with the EPA logo is removed. Requests a password if needed
83 All data is saved from the temporary stack to CMOS
84 Displaying Initializing Plug and Play Cards message
85 USB initialization complete
87 SYSID tables are created in the DMI area
89 ACPI tables are being installed. Interrupts are assigned to PCI devices
8B Called by the BIOS of additional ISA or PCI controllers, except
video adapter
8D Sets RAM parity parameters using CMOS Setup. Initialized
APM
8F IRQ 12 is allowed for hot plugging of a PS/2 mouse
94 Completion of chipset initialization. Displays the resource allocation table.
Enable L2 cache. Setting the summer/winter time transition mode
95 Sets the keyboard auto-repeat frequency and Num Lock state
96 For multiprocessor systems, registers are configured (for Cyrix processors).
The ESCD table is created. The DOS Time timer is set according to the clock readings
RTC CMOS.
Boot device partitions are saved for use by the built-in
antivirus.
The speaker announces the end of POST. MSIRQ table is created
FF BIOS INT 19h interrupt is in progress. Search for bootloader in the first sector
boot device





A shortened procedure is performed by setting the Quick Power On Self Test option in the BIOS.

65 The video adapter is being reset. The sound controller and devices are initialized
input/output, keyboard and mouse are tested. BIOS integrity is checked
66 Cache is initializing. An interrupt vector table is created.
The power management system is initializing
67 The CMOS checksum is checked and the battery is tested.
The chipset is configured based on CMOS parameters
68 Video adapter is initializing
69 Configuring the interrupt controller
6A Testing RAM (accelerated)
6B Displays EPA logo, CPU and memory test results
70 A prompt to enter BIOS Setup is displayed. The mouse is initialized
connected to PS/2 or USB
71 Cache controller is initializing
72 Chipset registers are being configured. A list of Plug and Play devices is created.
The drive controller is initializing
73 Hard disk controller is initializing
74 Coprocessor is initializing
75 If necessary, the hard drive is write-protected
77 If necessary, a password is requested and messages Press F1 to continue are displayed,
DEL to enter Setup
78 Expansion cards with their own BIOS are initialized
79 Platform resources are initializing
7A The root table RSDT, device tables DSDT, FADT, etc. are generated.
7D Collects information about boot device partitions
7E BIOS is preparing to boot the operating system
7F The NumLock indicator status is set according to the settings
BIOS Setup
80 INT 19 is called and the operating system starts
******************************************

AMIBIOS 8.0

D0 Initialization of the processor and chipset. Verifying boot block checksums
BIOS
D1 Initialization of I/O ports. Keyboard controller
a command is sent for BAT self-test
D2 Disable L1/L2 cache. The amount of installed RAM is determined
D3 Memory regeneration schemes are configured. Allowed to use cache memory
D4 Test 512 KB memory. The stack is installed and the communication protocol is assigned
with cache memory
D5 BIOS code is unpacked and copied to shadow memory
D6 Checks BIOS checksums and pressing Ctrl+Home keys
(BIOS recovery)
D7 Control is transferred to the interface module, which unpacks the code into the area
Run-Time
D8 The executable code is unpacked from flash memory into operational memory. Saved
CPUID information
D9 The unpacked code is transferred from the temporary storage area to the segments
0E000h and 0F000h RAM
DA CPUID registers are restored. POST execution is moved to RAM
E1–E8, EC–EE Errors related to the system memory configuration
03 Processing of NMI, parity errors, and output of signals to the monitor is prohibited.
An area is reserved for the GPNV event log, the initial
BIOS variable values
04 Checks battery health and calculates CMOS checksum
05 The interrupt controller is initialized and the vector table is built
06 The timer is being tested and prepared for operation
08 Keyboard testing (keyboard lights flashing)
C0 Initial processor initialization. Do not use cache memory.
Defined by APIC
C1 For multiprocessor systems, the processor responsible for starting the system is determined
C2 Completes the assignment of the processor to start the system. Identification with
using CPUID
C5 The number of processors is determined and their parameters are configured
C6 Initializes cache memory for faster POST.
C7 Processor initialization completes
0A Keyboard controller detected
0B Search for a mouse connected to the PS/2 port
0C Checking for keyboard presence
0E Various input devices are detected and initialized
13 Initial initialization of chipset registers
24 Platform-specific BIOS modules are unpacked and initialized.
An interrupt vector table is created and interrupt processing is initialized.
2A The DIM mechanism identifies devices on local buses. Preparing for
video adapter initialization, resource allocation table is built
2C Detection and initialization of the video adapter, the video adapter is called by the BIOS
2E Finding and initializing additional I/O devices
30 Prepares for SMI processing
31 ADM module is initialized and activated
33 The simplified loading module is initializing
37 AMI logo, BIOS version, processor version, login key prompt is displayed
in BIOS
38 Using DIM, various devices on local buses are initialized
39 DMA controller is initializing
3A Sets the system time according to the RTC clock
3B RAM is tested and results are displayed
3C Chipset registers are configured
40 Serial and parallel ports are initialized, mathematical
coprocessor, etc.
52 Based on the results of the memory test, the RAM data in CMOS is updated
60 BIOS Setup sets the NumLock state and configures the parameters
auto-repeat
75 The procedure for working with disk devices is started (interrupt INT 13h)
78 A list of IPL devices is created (from which the operating system can be loaded)
7C ESCD extended system configuration tables are created and written to NVRAM
84 Log errors encountered during POST
85 Messages are displayed about detected non-critical errors.
87 If necessary, BIOS Setup is launched, which is first unpacked into RAM
8C Chipset registers are configured in accordance with BIOS Setup
8D ACPI tables are built
8E Configures non-maskable interrupt (NMI) service
90 SMI is finally initialized
A1 Clearing data that is not needed when loading the operating system
A2 EFI modules are prepared to interact with the operating system
A4 According to BIOS Setup, the language module is initialized
A7 The POST procedure summary table is displayed
A8 Sets the state of the MTRR registers
A9 If necessary, waits for keyboard commands to be entered
AA Removes POST interrupt vectors (INT 1Ch and INT 09h)
AB Devices for loading the operating system are detected
AC The final stages of setting up the chipset in accordance with BIOS Setup
B1 ACPI interface is configured
00 Interrupt processing INT 19h is called (boot sector search, OS loading)

******************************************

PhoenixBIOS 4.0

02 Verify Real Mode
03 Disable Non-Maskable Interrupt (NMI)
04 Get CPU type
06 Initialize system hardware
08 Initialize chipset with initial POST values
09 Set IN POST flag
0A Initialize CPU registers
0B Enable CPU cache
0C Initialize caches to initial POST values
0E Initialize I/O component
0F Initialize the local bus IDE
10 Initialize Power Management
11 Load alternate registers with initial POST values
12 Restore CPU control word during warm boot
13 Initialize PCI Bus Mastering devices
14 Initialize keyboard controller
16 (1-2-2-3) BIOS ROM checksum
17 Initialize cache before memory autosize
18 8254 timer initialization
1A 8237 DMA controller initialization
1C Reset Programmable Interrupt Controller
20 (1-3-1-1) Test DRAM refresh
22 (1-3-1-3) Test 8742 Keyboard Controller
24 Set ES segment register to 4 GB
26 Enable A20 line
28 Autosize DRAM
29 Initialize POST Memory Manager
2A Clear 512 KB base RAM
2C (1-3-4-1) RAM failure on address line xxxx
2E (1-3-4-3) RAM failure on data bits xxxx of low byte of memory bus
2F Enable cache before system BIOS shadow
30 (1-4-1-1) RAM failure on data bits xxxx of high byte of memory bus
32 Test CPU bus-clock frequency
33 Initialize Phoenix Dispatch Manager
34 Disable Power Button during POST
35 Re-initialize registers
36 Warm start shut down
37 Re-initialize chipset
38 Shadow system BIOS ROM
39 Re-initialize cache
3A Autosize cache
3C Advanced configuration of chipset registers
3D Load alternate registers with CMOS values
40 CPU speed detection
42 Initialize interrupt vectors
45 POST device initialization
46 (2-1-2-3) Check ROM copyright notice
48 Check video configuration against CMOS
49 Initialize PCI bus and devices
4A Initialize all video adapters in system
4B QuietBoot start (optional)
4C Shadow video BIOS ROM
4E Display BIOS copyright notice
50 Display CPU type and speed
51 Initialize EISA board
52 Test keyboard The keyboard is being tested
54 Set key click if enabled
55 Initialize USB bus
58 (2-2-3-1) Test for unexpected interrupts
59 Initialize POST display service
5A Display prompt “Press F2 to enter SETUP”
5B Disable CPU cache
5C Test RAM between 512 and 640 KB
60 Test extended memory
62 Test extended memory address lines
64 Jump to UserPatch1
66 Configure advanced cache registers
67 Initialize Multi Processor APIC
68 Enable external and CPU caches
69 Setup System Management Mode (SMM) area
6A Display external L2 cache size
6B Load custom defaults (optional)
6C Display shadow-area message
6E Display possible high address for UMB recovery
70 Display error messages Error messages are displayed
72 Check for configuration errors
76 Check for keyboard errors
7C Set up hardware interrupt vectors
7D Initialize hardware monitoring
7E Initialize coprocessor if present
80 Disable onboard Super I/O ports and IRQs
81 Late POST device initialization
82 Detect and install external RS232 ports
83 Configure non-MCD IDE controllers
84 Detect and install external parallel ports
85 Initialize PC-compatible PnP ISA devices
86 Re-initialize onboard I/O ports
87 Configure Motheboard Configurable Devices (optional)
88 Initialize BIOS Data Area
89 Enable Non-Maskable Interrupts (NMIs)
8A Initialize Extended BIOS Data Area
8B Test and initialize PS/2 mouse
8C Initialize floppy controller
8F Determine number of ATA drives (optional)
90 Initialize hard-disk controllers
91 Initialize local-bus harddisk controllers
92 Jump to UserPatch2
93 Build MPTABLE for multi-processor boards
95 Install CD ROM for boot
96 Clear huge ES segment register
97 Fixup Multi Processor table
98 (1-2) Search for option ROMs. One long, two short beeps on checksum failure
99 Check for SMART Drive (optional)
9A Shadow option ROMs
9C Set up Power Management
9D Initialize security engine (optional)
9E Enable hardware interrupts
9F Determine number of ATA and SCSI drives
A0 Set time of day
A2 Check key lock
A4 Initialize Typical rate
A8 Erase F2 prompt
AA Scan for F2 key stroke
AC Enter SETUP
AE Clear Boot flag
B0 Check for errors
B2 POST done – prepare to boot operating system
B4 (1) One short beep before boot
B5 Terminate QuietBoot (optional)
B6 Check password (optional)
B9 Prepare Boot
BA Initialize DMI parameters
BB Initialize PnP Option ROMs
BC Clear parity checkers
BD Display MultiBoot menu
BE Clear screen (optional)
BF Check virus and backup reminders
C0 Try to boot with INT 19
C1 Initialize POST Error Manager (PEM)
C2 Initialize error logging
C3 Initialize error display function
C4 Initialize system error handler
C5 PnPnd dual CMOS (optional)
C6 Initialize notebook docking (optional)
C7 Initialize notebook docking late
D2 Unknown interrupt
E0 Initialize the chipset
E1 Initialize the bridge
E2 Initialize the CPU
E3 Initialize system timer
E4 Initialize system I/O
E5 Check force recovery boot
E6 Checksum BIOS ROM
E7 Go to BIOS
E8 Set Huge Segment
E9 Initialize Multi Processor
EA Initialize OEM special code
EB Initialize PIC and DMA
EC Initialize Memory type
ED Initialize Memory size
EE Shadow Boot Block
EF System memory test
F0 Initialize interrupt vectors
F1 Initialize Real Time Clock
F2 Initialize video
F3 Initialize System Management Mode
F4 (1) Output one beep before boot
F5 Boot to Mini DOS
F6 Clear Huge Segment
F7 Boot to Full DOS

A POST card or POST tester is a PCI expansion card that has a digital indicator that displays motherboard initialization codes. Using this code, you can find which of the board components has a malfunction. The codes often depend on the BIOS manufacturer. If there are no errors and the test is successful, then POST produces a code that does not change the value, for example, on most motherboards
When initialization is completed, the code “FF” is displayed. Testers are also often equipped with LEDs that display voltages +5 +3.3 +12, −12.

Here are the error codes suitable for most BIOS versions:

POST code	Description
D0	Pre-initialization of the motherboard and processor chipset. Checking the BIOS checksum. Disable non-maskable NMI interrupt. The Super I/O controller is being checked and the CMOS is being checked.
D1	The keyboard controller performs a self-test (BAT test). Initial initialization of the I/O ports is performed. Initializing the DMA controller.
D2	Disable the use of cache memory. The procedure for determining the amount of installed RAM is performed.
D3	The generation of requests for dynamic RAM regeneration is checked. Enable the use of cache memory.
D4	Testing 512 KB of memory. The stack address is set and the cache memory is configured.
D5	The system BIOS code is unpacked and rewritten into Shadow RAM.
D6	The BIOS checksum is calculated and the Ctrl+Home key combination is checked. If at least one of these conditions is met, the BIOS recovery procedure starts.
D7	If the BIOS checksums are successfully verified, control is transferred to the InterfaceModule, which unpacks the executable code into the Run-Time area.
D8	The Run-Time code is unpacked from flash memory into RAM. The CPUID information is stored in RAM.
D9	The unpacked Run-Time code is transferred from the temporary storage area to RAM. Control is transferred to the unpacked module.
D.A.	The CPUID registers are being restored. The POST procedure is in progress.
E0	Initializing floppy drive controller registers. The interrupt controller is initialized and interrupt vectors are set. Enable L1 cache.
E9	Setting up floppy drive registers.
E.A.	The read operation from ATAPI CD-ROM and disk memory is checked.
E.B.	Return to checkpoint E9 in case of errors during operations with ATAPI CD-ROM.
E.F.	Return to EB checkpoint if errors occur during disk operations.
F0	It looks for a recovery file named AMIBOOT.ROM.
F1	A transition is made to point F1 if the recovery file is not found.
F5	Disable L1 cache.
FB	FlashROM type definition. Search the FlashROM for a section for storing chipset settings.
F4	A transition is made to point F4 if the recovery file named AMIBOOT.ROM has an incorrect size.
F.C.	Resetting the main Flash BIOS block.
FD	The main Flash BIOS block is being programmed.
FF	The FF point is moved to if Flash BIOS programming has been successfully completed. Writing to FlashROM is prohibited. ATAPI hardware is being disabled. The CPUID value is restored.
03	Processing of non-maskable interrupts (NMI) and checking of RAM parity errors are prohibited. The data area of ​​the current BIOS execution and POST is being initialized.
04	Checking the CMOS checksum and battery voltage.
05	The interrupt controller is initialized and the interrupt vector table is generated.
06	Preparing for the interval timer to work.
08	The keyboard controller performs a self-test (BAT test). Initializing the CPU.
C0	Disable the use of cache memory. APIC controller initialization. Preparing the processor for operation.
C1	Configuring processor operation parameters.
C2	Identifying the processor using the CPUID command.
C5	Determining the number of processors and setting their parameters.
C6	Initializing the processor cache.
C7	Completing the initialization process of the central processor.
0A	Initializing the keyboard controller.
0B	Searches for a mouse connected via the PS/2 interface.
0C	Searching for a keyboard.
0E	Finding and initializing I/O devices. Interrupt capture INT 09h. Displays the BIOS logo on the screen.
13	The initial initialization of the chipset registers is performed.
24	The BIOS modules are unpacked and initialized. Preparing to initialize the interrupt vector table.
25	Completed initialization of the interrupt vector table.
2A	Devices are initialized on local buses (using the DIM-Device Initialization Manager mechanism). Preparing to initialize the video adapter.
2C	Finding and initializing the video card.
2E	Additional I/O devices are searched for and initialized.
30	The SMI (System Management Interrupt) component is initializing.
31	Unpacking the ADM module. Initialization and activation of ADM.
33	Initializing the bootloader module.
37	Displays the AMI logo, information about the BIOS version, information about the type of processor and its speed on the monitor screen. Displays on the monitor the name of the key that can be used to enter Bios Setup.
38	Devices are initialized on local buses (using the DIM-Device Initialization Manager mechanism).
39	The DMA controller is initializing.
3A	Set the system time according to the Real Time Clock (RTC).
3B	The RAM is tested and the test results are then displayed on the monitor.
3C	Setting up chipset registers.
40	The math coprocessor, parallel and serial ports are initialized.
50	The memory control modules are being adjusted.
52	The information in CMOS about the amount of RAM is adjusted (according to the results of the RAM test).
60	Programming the keyboard controller for the auto-repeat frequency and the waiting time before entering auto-repeat mode according to the BIOS Setup settings. Setting the state of the Numlock indicator according to the BIOS Setup settings.
75	The INT 13h interrupt is being initialized, which is used to work with disk devices.
78	A list of devices from which you can boot the OS is created.
7A	The remaining BIOS extensions are being initialized.
7C	Creating and saving the ESCD table.
84	A report is being compiled on errors that were detected during the POST procedure.
85	Displays information on the monitor about errors detected during the POST procedure.
87	At this stage, it is possible to enter the BIOS Setup program.
8C	Setting up chipset registers.
8D	The ACPI table is being built.
8E	Maintenance of NMI interrupts. Configuring peripheral device parameters.
90	Final SMI initialization in progress
A0	Request for a boot password (if this is provided in the BIOS Setup settings).
A1	This clears data that is not required to boot the OS.
A2	Preparing EFI modules.
A4	The language module is initializing.
A7	Displaying a table of the final results of completing the POST procedure.
A8	Programming MTRR (Memory Type Range Register) registers.
A9	Waiting for keyboard commands to be entered.
A.A.	Resetting interrupts INT 1C, INT 09. Disabling the procedure maintenance module (ADM).
AB	Determining devices from which you can boot the OS.
A.C.	The final stage of initializing the chipset registers in accordance with the BIOS Setup parameters
B1	The ACPI interface is being configured.
00	Performing BIOS INT 19h interrupt. Control of the boot process is transferred to the operating system loader. The OS starts loading.

Sound signals
The built-in speaker produces error codes during POST. Not all desktop boards have a built-in speaker, so a beeper must be connected.

BIOS Error Messages

Error message	Description
A processor has been detected that is not intended for use with this motherboard. Using unsupported processors may result in incorrect operation, damage to the desktop board or processor, or reduced service life. The system will turn off after 10 seconds.	The installed processor is not compatible with the desktop board.
CMOS Battery Low	The battery may be low. Replace the battery.
CMOS Checksum Bad	Error checking RAM checksum. The CMOS memory may be damaged. Run the BIOS Setup program to update the values.
Memory Size Decreased	The amount of memory has decreased since the last boot. If the memory modules have not been removed, the memory may be faulty.
No "Boot" Device Available	The system did not find a boot device.

Port 80h POST codes
During the POST test, the BIOS generates pass codes (POST codes) and sends them to I/O port 80h. If the POST procedure fails, the last generated POST code remains on port 80h. This code can be used to determine the cause of the error.

Displaying POST codes
You can use one of the following methods to display POST codes.

Port 80h POST code ranges
In the tables below, all POST codes and values ​​are presented in hexadecimal format.

Range	Category/Subsystem
00 – 0F	Debug Codes: Can be used as a debugging tool for any PEIM module/driver
10 – 1F	System processors
20 – 2F	Memory/chipset
30 – 3F	Recovery
40 – 4F
50 – 5F	I/O buses: PCI, USB, ISA, ATA, etc.
60 – 6F	Not currently used
70 – 7F	Output Devices: All output consoles
80 – 8F	Reserved for future use (for new output console codes)
90 – 9F	Input Devices: Keyboard/Mouse
A0–AF	Reserved for future use (for new input console codes)
B0–BF	Boot devices: Includes fixed and removable media.
C0–CF	Reserved for use
D0–DF
E0–FF	E0 – EE: Other codes F0 - FF: FF - processor interrupt error

Port 80h POST codes

POST code	POST Operation Description
00 - 0F	Debug Codes: Can be used as a debugging tool for any PEIM module/disk
10 - 1F	System processor
10	Enabling the system processor (boot processor)
11	Initializing the processor cache (including SP)
12	Start initializing processor applications
13	SMM initialization
14	Initializing a network connection
15	Premature exit when initializing platform driver
16	Initializing the SMBUS driver
17	Entering SMBUS executable code in read/write mode
19	Entering the CK505 clock generator programming mode
1F	Unrecoverable processor error
20 - 2F	Memory/chipset
21	Initializing Chipset Components
22	Reading SPD through DIMMs
23	Identifying DIMMs
24	Programming Clock Settings Using the Memory Controller and DIMMs
25	Memory configuration
26	Optimizing memory settings
27	Memory initialization, such as ECC
28	Memory testing
2F	The system was unable to detect memory or usable memory
30 - 3F	Recovery
30	Failure recovery was initiated at the user's request
31	Recovery after a software failure was launched (flash device damaged)
35	Transferring control to the recovery capsule
3F	Unable to recover
50 - 5F	I/O buses (PCI, USB, ISA, ATA, etc.)
50	PCI bus numbering
51	Transferring resources to the PCI bus
52	Initializing the Hot Plug PCI Controller
53 – 57	Reserved for PCI bus
58	Reinstalling the USB bus
59	Reserved for USB
5A	Reinstalling the PATA/SATA bus and all devices
5B	Reserved for ATA
5C	Reinstalling SMBUS
5D	Reserved for SMBUS
5F	Unrecoverable I/O bus error
60 - 6F	There are currently no valid POST codes in the range 60 - 6F. If the POST code is displayed in this range, it is a code from the range B0 - BF.(On a 7-segment LCD, the 'b' character appears as a 6). Example:
70 - 7F	Output devices
70	Reinstalling the VGA controller
71	Disabling the VGA controller
72	Enabling the VGA Controller
78	Reinstalling the Console Controller
79	Disabling the Console Controller
7A	Enabling the Console Controller
7F	Unrecoverable output device error
90 - 9F	Input Devices
90	Reinstalling the keyboard
91	Disabling the keyboard
92	Keyboard Presence Detection
93	Enabling the keyboard
94	Clearing the Keyboard Input Buffer
95	Keyboard Controller Information - Run Self Test (PS2 only)
98	Reinstalling the mouse
99	Disabling mouse
9A	Mouse Presence Detection
9B	Enabling the mouse
9F	Unrecoverable input device error (keyboard or mouse)
B0–BF	Boot devices
B0	Reinstalling desktop media
B1	Disabling stationary media
B2	Detecting the presence of stationary media (IDE hard drive detection, etc.)
B3	Connecting/configuring desktop media
B8	Reinstalling removable media
B9	Disabling removable media
B.A.	Detection of the presence of removable media (IDE detection, CD-ROM, etc.)
B.C.	Connecting/configuring removable media
B.F.	Unrecoverable boot device error
D0–DF	Boot device selection
Dy	Reboot via parameter y (y=0 to 15)
E0–FF	Other codes
E0	PEIM allocation started (occurs on first message EFI_SW_PC_INIT_BEGIN EFI_SW_PEI_PC_HANDOFF_TO_NEXT)
E2	Persistent Memory Detected
E1, E3	Reserved for PEI/PEIM
E4	Start of DXE phase
E5	Start of driver distribution
E6	Start connecting drivers
E7	Waiting for user data
E8	Password verification
E9	Entering the BIOS Setup utility
E.B.	Calling installed option ROMs
F4	Entering sleep mode
F5	Wake up from sleep mode
F8	An EFI boot service call has occurred ExitBootServices()
	The EFI work execution service SetVirtualAddressMap() was called
F.A.	A call to the EFI run service ResetSystem() occurred
FF	CPU error

Typical port 80th POST sequence
Typically the 80h port codes are incremented during the boot process. Smaller code values ​​refer to subsystems located closer to the processor, and larger code values ​​refer to peripheral devices. Typically the following initialization order is used: Processor -> Memory -> Buses -> I/O Devices -> Boot Devices. The sequence of POST codes depends on the system used.

13Initializing SMM50Numbering PCI buses51Transferring resources to the PCI bus92Detecting the presence of the keyboard90Reinstalling the keyboard94Clearing the keyboard input buffer95Keyboard self-testEBCalling BIOS graphics modes58Reinstalling the USB bus5AReinstalling the PATA/SATA bus and all devices92Detecting the presence of the keyboard90Reinstalling the keyboard94Clear Keyboard input buffer5AReinstalling the PATA/SATA bus and all devices28Memory testing90Reinstalling the keyboard94Clearing the keyboard input bufferE7Waiting for user data input01INT 1900Ready for reboot

POST-codesAward BIOS Medallion V 6.0

POST code (hex) Check completed

Performing POST startup procedures from Flash BIOS

CF Early detection of processor type. Recording results in CMOS. CMOS read/write functional test.

If processor type detection or CMOS writing fails, a fatal operation error is set and POST execution is stopped.

C0 Chipset pre-initialization.

Prohibition of shadow RAM areas, disabling L2 cache. Clear L1 cache.

Programming the following basic chipset registers.

• Interrupt controllers: receive on IRQ edge, Master Controller - IRQ 00h=INT 8...IRQ 7=INT 0Fh, Slave Controller - IRQ 8= INT 70h...IRQ 15=INT 77h.

• DDP controllers.

• Interval timer: Counter 0 - frequency division mode by 65,536 (18.2 Hz) to generate IRQ 0 system clock requests. Counter 1 - generation of pulses for DRAM regeneration (128 cycles are performed in 2 ms or the interval between regeneration of two lines is about 15 μs). Counter 2 - used to sound the system speaker.

• The RTC is initialized if there is a battery power failure. If there was no Vcc (bat) failure, then only the registers responsible for the interaction between the RTC and the processor are initialized, but not the clock

	Checking the type, size, high address and ECC of RAM. Checking the first 256 KB of RAM.
	Organization in this area of ​​a transit buffer, into which from Flash BIOS
	Boot Block is copied to verify checksums
	Checking the BIOS checksum and the presence of the BBSS tag. If the checks are incorrect,
	a decision is made about partial damage to the Flash BIOS IC. If checks
	are correct, the system BIOS unpacking program is copied to the buffer
	Unpacking the system BIOS into RAM, copying the optional system into RAM
	BIOS. Preparing for BIOS Shadowing
	Copy the executable POST code to the shadow RAM area E000h-F000h.
	Transfer control to the Boot Block module.
	Start POST from shadow RAM.

Checking the integrity of the BIOS structure. If the checksums for checking the BIOS service fields match, the RAM check continues, otherwise control is transferred to the BIOS recovery programs

Performing POST on Shadow RAM )

1 At physical address 1000:0000h, the BIOS module is unpacked - the XGROUP program, which allows you to set all the resources of the motherboard, including the system timer, interrupt controllers and DMAs, a mathematical coprocessor and a default video controller

3 Performing early initialization of the Super I/O chip, the first stage was performed in algorithm steps CFh and C0h

5 Setting the initial attributes of the video system.

Checking the CMOS status flag, its contents are reset

7 Reset the input and output buffers of the keyboard controller (8042 or 8742 compatible). The controller is part of the Super I/O system chip

fees. Self-test, initialization of the keyboard controller. Keyboard interface connection allowed

	Prohibition of connecting the PS/2 computer mouse interface.
	The type of keyboard interface is determined (PS/2 or AT/DIN). Programmable
	keyboard controller. Keyboard allowed
	The PS/2 mouse interface is still disabled.
	For some systems - determining the ports to which the PS/2 keyboard is connected
	and mouse, which may cause port reassignment
	Checking the shadow segment F000h with read and write cycles. This area
	will be used for DMI and ESCD. If the check is incorrect, then
	a sound signal is generated and error code EFh is output to port 0080h
	If the written and read data from the F000h segment do not match,
	an error is detected and the POST execution is stopped

10 Determining the type of installed Flash BIOS. The check allows you to select the appropriate writing program for the BIOS, with the help of which a special Read Intelligent Identifier command is loaded. The command is also used by the procedures for modifying ESCD and DMI blocks, which can be overwritten both during boot and after it - when applications access the Plug and Play or DMI functions.

BIOS code executed in a work session will be decoded and written to the Run-time area (F000h).

Programming chipset registers

12 Perform a chain of CMOS tests. The RTC clock is set to power mode. CMOS cells are subsequently used to store intermediate results during the initialization procedure. In particular, default values ​​are loaded into cells

14 Perform early chipset initialization. At the first stage, resources that are not available to the motherboard developer are programmed. At the second stage, the values ​​changed using the MODBIN utility are loaded into the chipset registers. Fine-tuning of RAM and PCI devices becomes possible

16 Early initialization of the system clock - setting to default values

18 Determination of processor parameters: manufacturer, family, generation, determination of the type and size of L1 and L2 cache, SMI type. Performing the function of the CPUID command (codes and architecture of processors from different manufacturers differ).

Checking processor registers, measuring processor core clock speed. After executing the function, the result is placed in a 128-bit word formed by the register cells of the central processor - EAX + EBX + ECX + EDX. To decrypt the value of the cache being used, the code is shifted and moved to the AL register

	Initialization of the interrupt vector table (volume 1,024 bytes, 256 types
	interrupts). At this stage, the types for 32 vectors are established (INT 00h-
	INT 1Fh), indicating BIOS procedures.
	Performing checks to ensure Y2K compliance
	Checking CMOS checksum and supply voltage compliance
	battery nominal. If errors are detected, the values ​​are set according to
	defaults set by the motherboard manufacturer

At this stage, receiving scan codes from the keyboard and processing them by the 8742 controller and processor is impossible, since interrupts are disabled, the BIOS data area is not prepared, and the keyboard is not initialized. Setup BIOS settings must not conflict with the execution of the POST sequence

21 Initializing the Hardware Power Management system for laptops.

Formation of a table of physical parameters, a structure for servicing autonomous battery power, energy-saving functions when operating hard drives, as well as operations for saving a RAM image on a disk

23 Math coprocessor detection.

Checking the number of cylinders - 40 or 80, as well as the type of floppy disk installed.

Perform early chipset initialization.

Preparing a BIOS resource map intended for further installation of Plug and Play devices, as well as airborne devices on the PCI bus

24 Processors of the Intel P6 and P7 generations provide the ability to organize access to microprogram memory, which contains algorithms for executing each machine command. At this stage, changes can be made to the firmware microcode to modernize the algorithms or introduce new microcodes designed for new machine instructions. The microcode update procedure is as follows.

• Using the CPUID command, the processor is identified and its parameters are determined - Type, Family, Model and Stepping.

• The required block of 2,048 bytes is read from the microcode update module stored in the BIOS and unpacked not into RAM, but into SM RAM.

• The processor microcode is updated.

Some Intel processors require additional identification. The resource distribution map is being updated

Plug and Play devices are initialized. Information about resources requested by Plug and Play devices is updated based on scanning data from CMOS, BIOS extensions located on the expansion buses, as well as information stored in the ESCD data block. Writing data to ESCD is deferred until the final stage of POST execution

25 Early PCI initialization. Enumeration of devices on the bus. Assignment of RAM and airborne resources.

Search for a video system device, BIOS extensions and write information to area C000:0h (segment address in the CS register: offset address in the IP register)

26 Configuring the logic that serves the Vendor Identification lines.

Completes system clock initialization. Disable synchronization of unused DIMM and PCI slots.

Initialization of the voltage and temperature monitoring system, performed according to the type of motherboard

At this stage, receiving scan codes from the keyboard and processing them by the 8742 controller and processor is impossible, since interrupts are disabled, the BIOS data area is not prepared, and the keyboard is not initialized. Setup BIOS settings must not conflict with the execution of the POST sequence

27 Interrupt enable INT 09h. Re-initialization of the keyboard controller based on new data (interrupt vector table, chipset initialization).

For the BIOS, a 16-character input buffer is formed and a memory area is set for full operation

29 Programming MTRR registers of the P6 generation processor, as well as initializing the APIC controller of Pentium processors.

	Programming the chipset (such as an IDE controller) according to
	with settings in CMOS.
	Measuring the internal processor frequency.
	Calling the video system BIOS extension
	Initializing the multilingual module.
	Sending data to be displayed on the display screen (Award screen saver, type
	processor and its speed)
	Super I/O Chip Programming
	Checking the masking bits of interrupt controller channel 1 (compatible

40 Checking the masking bits of channel 2 of the interrupt controller (compatible with IC 8259)

	Checking the functioning of the interrupt controller (compatible with IC 8259)
	Calculate total memory by checking each double word in each 64 KB page.
	Recording a program designed to test AMD family processors
	Programming MTRR registers of the Syrix family processor. Initialization
	L2 cache of P6 generation processors, as well as APIC initialization for P6
	USB bus initialization
	Check all memory, clear extended memory

55 For a multiprocessor platform, the number of processors is displayed

57 Displays the Plug and Play logo screen. Early provisioning of Plug and Play devices

59 Activating the anti-virus protection resource - the integrated anti-virus tool Trend Anti-Virus

60 Stage allowing you to load the Setup program.

Before this POST stage you must have time to press the appropriate key

65 Initializing a PS/2 computer mouse

67 Preparing information for the address space intended for the call function: INT 15h (contents of register AX=E820h)

At this stage, receiving scan codes from the keyboard and processing them by the 8742 controller and processor is impossible, since interrupts are disabled, the BIOS data area is not prepared, and the keyboard is not initialized. Setup BIOS settings must not conflict with the execution of the POST sequence

	Enabling L2 cache
	Programming chipset registers in accordance with the elements described
	in Setup and in the autoconfiguration table
	Assign resources to all Plug and Play devices.
	Automatic COM port allocation for integrated devices
	if the Setup option is set to “AUTO”
	Initializing the floppy disk controller.
	Additional configuration of floppy disk registers

73 Optional BIOS update utility input function AWDFLASH.EXE if it is on a floppy disk and the key combination is selected

75 Detection and installation of all IDE devices: hard drives, LS-120, ZIP, CD-R/RW, DVD, etc.

If an error is detected, a corresponding message is displayed and the program waits for a keystroke.

If no error is detected or a key is pressed , POST execution continues.

Cleaning the EPA or Manufacturer Logo Screen Saver

82 Depending on the type of chipset and motherboard, an area is allocated in RAM for power management.

The ESCD table is updated with the latest changes related to power management.

After removing the splash screen with the EPA logo, the video mode is restored. Request a password, if provided by CMOS settings

83 Restoring data from a temporary storage stack in CMOS

84 Displays the message “Initializing Plugand Play Cards...” about previously detected Plug and Play devices and parameters

85 USB initialization completed.

Determining boot order from SCSI hard drives

87 Switching the video system to text mode.

Construction of SYSID tables in the DNI area according to the “System Management BIOS” specification.

To serve network devices, a UUID (Universal Unique ID) is created, as well as an identifier for booting from Fire Wire IEEE 1394 devices

At this stage, all basic initialization procedures have been completed. Preparations are being made for loading the operating system, the tables necessary for this are compiled, arrays and structures are formed

89 If the Setup program allows the use of the ACPI protocol, the corresponding tables are inserted into the upper 4 GB address space

	Scanning in the PCI space for BIOS extensions designed for
	implementation of the AOL (Alert On LAN) protocol. Initializing AOL Tools
	Allowing the use of logical means to support unmasked
	NMI interrupts.
	Enable the use of RAM module parity
	For PS/2 mouse hot plugging, IRQ 12 is allowed.
	IRQ 11 line maintenance, normalization of line noise parameters
	interrupt requests

91 Preparing conditions for servicing hard drives in Power Management mode. Operations of this type (Suspend to RAM) can be implemented in a working session of the operating system.

Setting BIOS variables that store the base addresses of serial and parallel ports that host BIOS expansion programs

93 Preparing to save information about boot device partitions

94 If Setup is provided, the L2 cache is enabled. The Boot Up Speed ​​parameter is programmed.

Completing initialization of the chipset and power management system.

Removing the BIOS startup screen, a resource distribution table is displayed on the monitor screen.

Configuring registers for AMD K6 family processors. The final update of the registers of the Intel P6 family of processors.

Final initialization of the Remote Pre Boot subsystem

95 Setting the automatic transition to winter/summer time Daylight Saving.

Programming the keyboard controller for the number of keystrokes per second and the wait time before entering auto-repeat mode.

Reading keyboard KBD ID.

For a 101-key keyboard, the NumLock flag is set according to the CMOS information

96 Saving information about boot device partitions.

In multiprocessor systems, the final configuration of the system is performed, service tables and fields used in the working session of the operating system are formed.

Configuring registers for Cyrix family processors.

Filling and updating the ESCD table in accordance with the state of the Power Management system of Plug and Play and ATAPI devices.

Adjustment of CMOS in accordance with the requirements of the Y2K protocol.

Setting the system clock counter DOS Time in accordance with the RTC CMOS readings. The time value from the “hours:minutes:seconds” format is recalculated

in clock cycles (time intervals of pulse repetition) of the 18.2 Hz interval timer and is recorded in the BIOS variable area - DOS Time.

At this stage, all basic initialization procedures have been completed. Preparations are being made for loading the operating system, the tables necessary for this are compiled, arrays and structures are formed

Saving boot device partitions for future use by integrated antivirus tools Trend Anti-Virus and Paragon Anti-Virus Protection.

Enable the use of L1 cache.

A sound signal for the end of POST is generated on the system unit speaker. Building and saving the MSIRQ table.

Preparing to boot the operating system

FF Transfer control to the initial sector loader program BOOT. Performing BIOS INT 19h interrupt.

The called subroutine allows (in accordance with the BIOS Features Set Up menu option in the Setup program) to poll boot devices to search for the boot sector. To load information from the sector Cylinder: 0, Head: 0, Sector:

1 is read at address 07C0:0000h, after which control of the FAR JMP command is transferred to the beginning of this block

Executing a program written in the boot sector

NOTE.

ECC(Error Correcting Code) — error correction code used in RAM modules, contributing increasing PC fault tolerance. ECC allows error correction in one bit and detection in two bits. Therefore, a computer whose memory uses such codes can operate without interruption in the event of an error in one bit, and the data will not be distorted

BBSS(Boot Block Specification Signature) - Boot block specification signature label.

SMI(System Management Interrupt) - Hardware, integrated into the processor, designed to control power consumption. A high priority interrupt is used to service these components.

Y2K— requirements, requirements for commercial computer system products for ensuring interoperability, functionality and other parameters that occurred before and after 2000.

DMI(Desktop Management Interface) - protocol, allowing for interaction software with motherboard components.

MTRR(Memory Type Range Registers) - generation processor registers P6 And P7, in which Data is entered that describes the properties of memory areas and determines the type of memory caching.

APIC ( Advanced Programmable Interruption Controller) - advanced programmable interrupt controller, included in the chipset. Processor generation P6 Also has a similar controller for multiprocessor applications.

MSIRQ(Microsoft IRQ Routing Map) - table cards distribution interrupts, standardized by Microsoft.

SM RAM(System Management RAM) - one of the names for random access register memory small capacity provided in the processor architecture, starting with Pentium Pro and higher, intended for storing service data.

If each process fails adequately, the algorithm switches to special case processing and POST BIOS Medallion generates the codes noted below:

POST-codesspecialcasesAward BIOS V 6.0 Medallion

System Events codes

Code activated when servicing APM or ACPI components (Power Management Debug codes)

	Energy saving with +12 V supply voltage cut-off
	Switching to operating mode with minimal power consumption
	Interrupt to exit power saving mode by event
	Switching the processor into power saving mode by reducing its clock speed
	Switching to partial power saving mode using ACPI technology
	Using the SMI Component to Enter Power Saving Mode
	Putting the processor into power saving mode using APM technology
	Switching the system into power saving mode using APM technology
	Putting the system into full power saving mode

Message about fatal errors during operations (System Error codes)

	ECC code processing error
	Hard drive error when returning from power saving mode
	Data mismatch when writing to and reading from segment F000h

To reduce the time it takes to complete the POST Award BIOS test program, you can use the Quick Power On Self Test option, which can be found in the Setup program. In this case, a modified version of the Award Software test is launched, which, unlike the full version of the program, runs quickly.

POST AMI BIOS 8 V1.4 checkpoint codes

Understanding the Breakpoint Code Display

To display POST AMI BIOS checkpoints, POST Diagnostic Cards, indicators on system boards, and displays control AMI BIOS Checkpoint Display.

The display is a line of code in the lower right corner of the monitor screen that appears during POST.

The disadvantage of using the checkpoint code display is that it cannot be used when the video system is turned off.

Purpose of the Device Provisioning Manager

During various periods of POST testing, control is transferred to a special program DIM device initialization manager(Device Initialization Manager).

This program receives control from the BIOS if it is necessary to check the system or local buses of the computer. There are several POST checkpoints designed to run this program.

2Ah initialization of devices on the system bus.

38h initialization of IPL devices.

39h indication of errors during bus initialization.

95h initialization of buses controlled by BIOS extensions.

DEh - RAM configuration error.

DFh - RAM configuration error.

Messages generated by the DIM are also output to diagnostic port 80h and stored in the data word while the test is running.

The word in which the marked information is stored contains the low byte, which matches the system POST code. The high byte is divided into two tetrads. Below is a description of the codes loaded into notebooks.

Fields of the senior tetrad.

Initialization of all devices on the buses of interest is prohibited.

Initialize static devices on the buses of interest.

Initialization of information output devices on the buses of interest.

Initialization of information input devices on the buses of interest.

Initialize system load (IPL) devices on the buses of interest.

Initialization of general purpose devices on the buses of interest.

Error messages for the tires of interest.

Initialization of devices controlled by BIOS extensions (for all buses).

Initialize BIOS boot extensions that comply with the BIOS Boot Specification (for all buses).

Junior tetrad.

System initialization procedures (DIM).

Buses for connecting integrated system devices.

ISA bus Plug and Play.

PCMCIA bus.

If a RAM configuration error is detected, a cyclic sequence of codes DEh, DFh and configuration checkpoints is output to the diagnostic port, which can take the following values.

00 No RAM detected.

01 different types of DIMMs are installed.

02 Reading from the SPD (Serial Presence Detect) node of the DIMM failed.

03 DIMM cannot be used at this frequency.

04 DIMM cannot be used in this system.

05 error in the low memory page.