A conflict is a situation in which several objects simultaneously try to access a resource that is intended for only one of them. An interrupt conflict occurs when multiple devices use the same interrupt line to send a request signal and there is no mechanism to handle the concurrent requests. If the driver, receiving control, does not work with the device that sent the request, then either a failure occurs, or one of the devices simply does not work.

The question arises: can several devices use the same interrupt line, or is it impossible in principle? After all, if the driver is able to determine from whom exactly the request came, then it will respond to signals from only "its" device, ignoring all the others. But this must be agreed in advance in some way, otherwise the conflict is inevitable.

The local PCI bus was designed with interrupt sharing in mind. Each PCI device must work correctly on the same interrupt line with other PCI devices. This is done in the following way: the fact of the presence of a signal on the interrupt line is determined not by the edge, i.e. a change in the voltage level, but by the very fact of the presence of a certain voltage. Several devices can change the voltage in the line at once, becoming, as it were, in a queue for service.

Thus, the sharing of the same IRQ by several PCI devices is not a conflict by definition (Fig.). However, sometimes problems do arise. First, not all PCI devices work correctly on the same interrupt line with others. Secondly, sometimes drivers have errors due to which they cannot correctly determine the signal source, interfering with other drivers. Thirdly, not all devices operate on the PCI bus; for example, ISA devices, which include, for example, COM / LPT port controllers, cannot share interrupts with others.

Rice. Win2000 Device Manager IRQ Map - IO PIC Intel 440BX Chipset

Rice. Win2000 IRQ MAP - IO APIC - Via KT266a Chipset

As a result, situations are possible when the computer starts to freeze frequently, refuses to perform any functions, or even simply falls out into the so-called " blue screen of death".

Apic (Advanced Programmable Interrupt Controller)

As shown above, the interrupt line is a very scarce resource for a computer. However, with the development of the computer industry, the number of various external devices in the computer is constantly increasing. For example, one motherboard can have 5-6 PCI slots, AGP slot, built-in IDE controller, built-in SCSI controller, built-in 1/2-port network adapter, etc. And all these devices need interrupts. 16 IRQ lines gradually became not enough.

APIC Is an interrupt controller that allows you to use 24 hardware interrupts instead of 16. The limit of 16 hardware interrupts, unchanged since 1982, held back the installation of additional devices in a personal computer. At the end of 2001, the first motherboards with APICs appeared.

Rice. Interrupt system in a multiprocessor environment.

The previous description was for PICs designed for uniprocessor systems. If the system includes two or more processors, this approach is no longer permissible and more complex PICs are required.

Everything modern processors x86 include local APIC. Each local APIC has 32-bit registers, an internal clock, a local timer, and two additional IRQ lines, LINT0 and LINT1, reserved for local APIC interrupts. All local APICs are connected to an external I / O APIC.

The I / O APIC contains a set of 24 IRQ lines, a 24-input interrupt routing table, programmable registers and a message block for sending and receiving messages on the APIC bus. Unlike the IRQ pins of the 8259A, the interrupt priority is not tied to the pin number.

Each entry in the interrupt routing table can be programmed individually to display the interrupt vector and its priority, the processor that will handle the interrupt and how this processor will be selected. The information in the interrupt routing table is used to translate each external signal into a message addressed to one or more local APICs over the APIC bus.

Static distribution

The IRQ signal is delivered to the local APICs listed in the appropriate IRQ redirection table entry. An interrupt is delivered to one specific CPU, multiple CPUs, or all CPUs.

Dynamic allocation

The IRQ signal is delivered to the local APIC of the processor, which executes the process with the lowest priority.

Each local APIC has a programmable job priority register that is used to calculate the priority of the current process. Intel expects this register to be modified by the operating system kernel on every process switch.

In addition to distributing interrupts across processors, the multi-APIC system allows the CPU to generate interprocessor interrupts. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the target local APIC ID in the Interrupt Command Register (ICR) of its local APIC. The message is then sent via the APIC bus to the target local APIC, which issues the appropriate interrupt to its CPU.

Many uniprocessor systems currently include an I / O APIC chip that can be configured in two ways:

1. As a standard 8259A PIC linked to the CPU. Local APIC is disabled and the two lines LINT0 and LINT1 are configured as INTR and NMI pins.

2. As a standard external I / O APIC. Local APIC is enabled and all external interrupts are received through the I / O APIC.

• Alieva Elena Viktorovna, student
• Ufa State Aviation Technical University

• INTERRUPTION CONTROLLER
• CONTROLLER
• HARDWARE INTERRUPTIONS
• INTERRUPT

Interruption means the temporary interruption of the main computation process to perform some planned or unplanned actions caused by the operation of the hardware or program. The interrupt mechanism is supported at the hardware level. Hardware interrupts occur as a reaction of the microprocessor to a physical signal from some device (keyboard, system clock, keyboard, HDD etc.), these interrupts are asynchronous by the time of occurrence, i.e. occur at random times. The interrupt controller is designed to process and arbitrate incoming service requests to central processing unit from peripheral devices. Interrupts have a certain priority, which allows the interrupt controller to give preference to this moment time to one device, not another. In a modern computer, there are up to 16 external and peripheral devices that generate interrupts.

• Automation of document flow in a warehouse of a manufacturing enterprise
• Calls technologies, features, application and efficiency
• Development of a model of the information system of the legal department for the support and conclusion of contracts of the enterprise

Introduction

Interruption means the temporary interruption of the main computation process to perform some planned or unplanned actions caused by the operation of the hardware or program. Those. it is a process that temporarily switches the microprocessor to execute another program and then returns to the interrupted program. By pressing a key on the keyboard, we initiate an immediate call to the program that recognizes the key, puts its code into the keyboard buffer, from which it is read by another program. Those. the microprocessor interrupts the execution for a while current program and switches to the interrupt handler, the so-called interrupt handler. After the interrupt handler completes its work, the interrupted program will resume execution from the point where it was suspended. The address of the interrupt handler is calculated from the interrupt vector table.

The interrupt mechanism is supported at the hardware level. Depending on the source, interrupts are divided into:

• hardware- arise as a reaction of the microprocessor to a physical signal from some device (keyboard, system clock, keyboard, hard disk, etc.), these interrupts are asynchronous in time of occurrence, i.e. occur at random times;
• programmatic- are called artificially with the help of the corresponding command from the program (int), are intended to perform some actions of the operating system, are synchronous;
• exceptions- are the reaction of the microprocessor to a non-standard situation that has arisen inside the microprocessor during the execution of a certain program command (division by zero, interrupt by the TF flag (trace)).

Interrupt system hardware

An interrupt system is a collection of software and hardware that implements the interrupt mechanism.

Interrupt system hardware includes:

• microprocessor outputs - signals are generated on them that notify the microprocessor either that some external device "asks for attention" (INTR), or that urgent processing of some event or catastrophic error (NMI) is required
• INTR - pin for the interrupt request input signal,
• NMI - pin for non-maskable interrupt input signal
• INTA - output for the output signal of confirmation of receipt of the interrupt signal by the microprocessor (this signal is fed to the input of the same name of the 8259A controller microcircuit;
• 8259A programmable interrupt controller (designed to fix interrupt signals from eight different external devices; it is made in the form of a microcircuit; usually two serially connected microcircuits are used, so the number possible sources external interrupts up to 15 plus one non-maskable interrupt; it is he who forms the interrupt vector number and issues its data bus);
• external devices (timer, keyboard, magnetic disks etc.)

Interrupt handling

An interrupt triggers a series of events that occur in both the hardware and software... In fig. 1 shows a typical sequence of these events.

When the I / O device is finished, the following occurs:

• The device sends an interrupt signal to the processor.
• Before responding to an interrupt, the processor must complete the execution of the current command (see Fig. 1).
• The processor checks for the presence of an interrupt, detects it and sends the device that sent this interrupt, notifying a signal of successful reception. This signal allows the device to clear its interrupt signal.

Figure 1. Program Timing: Slow I / O

Now the processor needs to prepare to transfer control to the interrupt handler. You must first save all important information, so that later you can return to the place of the current program where it was paused. The minimum required information is the program status word and the address of the next executed command, which is located in the program counter. This data is pushed onto the system control stack.

Figure 2. Handling a simple interrupt

Further, the address of the input of the interrupt handler, which is responsible for processing this interrupt, is loaded into the program counter of the processor. Depending on the architecture of the computer and the device of the operating system, there may be either one program for processing all interrupts, or there may be a separate processing program for each device and each type of interrupt. If there are multiple programs available to handle interrupts, the processor must determine which one to call. This information may be contained in the original interrupt signal; otherwise, in order to obtain the necessary information, the processor must interrogate all devices in turn to determine which one sent the interrupt.

As soon as a new value is loaded into the program counter, the processor proceeds to the next instruction cycle, starting to retrieve it from memory. Since the command is retrieved from the location, the number of which is set by the contents of the program counter, control passes to the interrupt routine. The execution of this program entails the following operations.

The contents of the program counter and the status word of the program being interrupted are already stored in the system stack. However, this is not all the information pertaining to the state of the executable program. For example, you need to save the contents of the processor registers, as these registers may be needed by the interrupt handler. Therefore, it is necessary to save all information about the state of the program. Typically, an interrupt handler begins by writing the contents of all registers onto the stack. Other information that should be retained is discussed in Chapter 3, "Describing and Controlling Processes." In fig. a simple example is shown, in which the user program is interrupted after executing an instruction from cell N. The contents of all registers, as well as the address of the next instruction (N + 1), in total, making up M words, are pushed onto the stack. The stack pointer is then updated to point to the new top of the stack. The program counter is also updated to indicate the start of the interrupt routine.

The interrupt handler can now start its work. Interrupt handling includes checking status information related to I / O operations or other events that triggered the interrupt. This may also include sending additional instructions or notification messages to I / O devices.

After the completion of interrupt processing, the previously stored values ​​are popped from the stack, which are again put into the registers, thus resuming the state in which they were before the interrupt.

The last step is restoring the program status word and the contents of the program counter from the stack. As a result, the command of the interrupted program will be executed next.

Due to the fact that the interrupt is not a subroutine called from the program, it is important for a complete recovery to retain all the state information of the interrupted program. However, an interruption can occur at any time and anywhere in the user program. This event is unpredictable.

Interrupt controller

The interrupt controller is designed to process and arbitrate incoming service requests to the central processor from peripheral devices. By analogy, the function of the interrupt controller can be compared to the secretary of some boss. The secretary must decide which of the visitors to be admitted to the boss first, and who later, based on the priorities given by the boss and the status of the visitor himself. Likewise in a computer system, it is possible that several peripheral devices send an interrupt signal or an interrupt request. In computer literature, this signal is referred to as IRQ (Interrupt Request).

As mentioned above, interrupts have a certain priority, which allows interrupt controllers to give preference at a given time to one device over another. In a modern computer, there are up to 16 external and peripheral devices generating interrupts. These devices are:
–IRQ 0, system timer; –IRQ 1, keyboard; –IRQ 2, used to query devices connected in cascade; –IRQ 8, real time clock; –IRQ 9, reserved; –IRQ 10, reserved; –IRQ 11, reserved; –IRQ 12, ps / 2 – mouse; –IRQ 13, coprocessor; –IRQ 14, hard disk controller; –IRQ 15, reserved; –IRQ 3, ports COM2, COM4; –IRQ 4, ports COM1, COM3; –IRQ 5, port LPT2; –IRQ 6, floppy drive controller; –IRQ 7, LPT1 port, printer.

Here the signals are listed in descending order of priority. You can see that after IRQ 2, followed by IRQ 8. The fact is that at one time the interrupt controller consisted of two microcircuits, one was connected to the other. This second microcircuit is connected to the IRQ 2 line, forming a cascade. It serves lines IRQ8 – IRQ 15. And then the lines of the first microcircuit follow.

Interrupt controller operation

Interrupt controllers considered chip-based Intel 8259A, which were used in now very old computers with processors up to the 386 series. These computers usually had 2 8259A chips connected in cascade, that is, one to the other. One of the microcircuits connected via the interrupt request line directly to the processor is the master or master. The rest, connected to the master through similar pins, are called slaves.

Figure 3. Wiring diagram of interrupt controllers and their interaction with the central processor

Figure 3 shows the connection diagram of interrupt controllers and their interaction with the central processor. Interrupt signals from peripheral devices or slave controllers are sent to the inputs IR0 – IR7 of the master controller. The internal logic of the master controller processes the incoming requests in terms of priority. If the priority of the device request is sufficient, then a signal is generated at the INT output of the controller, which is fed to the INTR input of the processor. Otherwise, the request is blocked.

If the processor allows interrupts, then after completing the execution of the current command, it generates a sequence of signals on the INTA line that puts the slave controller into a state of immunity to incoming new interrupt requests, and in addition, information from the internal registers of the controller is output to the data line from the internal registers of the controller by which the processor recognizes the type of interrupt.

The processor transfers the interrupt permission to the interrupt controller via the bus controller. The RD signal is intended for the interrupt controller to place the contents of the internal registers on the data bus. On the WR signal, the interrupt controller, on the contrary, receives data from the bus of the same name and writes it to the internal registers. Accordingly, this affects the mode of operation of the interrupt controller.

The CS input is connected to the address bus and this signal is used to identify a specific interrupt controller. Input A0 points to the interrupt controller port in I / O space.

Inputs IR0 – IR7 are designed to receive interrupt requests from peripheral devices and slave controllers.

Outputs CAS0 – CAS2 are designed to identify a specific slave controller.

The article discusses hardware interrupts and device, functions, operation of the interrupt controller. This controller interrupts appeared in the first PC-compatible computers. Since then, both the processors and the computer itself have changed a lot, although some points have remained. Therefore, in order to make it clearer and the organization of the 8295A interrupt controller was considered.

The above diagram shows signals coming not only to the slave and master interrupt controllers, but also to the other slaves. However, your computer or laptop actually has 2 interrupt controllers as stated above: master and slave. But you can create your own computer systems thus using up to 64 slave interrupt controllers.

In modern computers for a long time interrupt controller functions it is not performed by the 8259A microcircuits, but by the south bridge. However, for all programs and devices, everything remains the same. Moreover, the interrupt controller is programmable, and the internal registers and ports must be accessed in the same way as the 8259A controller.

Conclusion

In this paper, interrupts were considered, namely the hardware interrupt handling and the principle of interrupt handling. Also considered interrupt controllers and their principle of operation.

Interruption means the temporary interruption of the main computation process to perform some planned or unplanned actions caused by the operation of the hardware or program. The interrupt mechanism is supported at the hardware level. Hardware interrupts occur as a microprocessor's response to a physical signal from a device (keyboard, system clock, keyboard, hard disk, etc.); these interrupts are asynchronous in time of occurrence, i.e. occur at random times.

Interrupt controller designed to process and arbitrate incoming service requests to the central processor from peripheral devices. Interrupts have a certain priority, which allows interrupt controller give preference at a given time to one device over another. In a modern computer, there are up to 16 external and peripheral devices that generate interrupts.

Bibliography

1. Lecture. Interrupts. Email Resource. http://hromatron.narod.ru/_lekcii/prerivania_lekcia_g2013.htm
2. System Interrupts | Hardware interrupt | Interrupt handling http://life-prog.ru/view_os.php?id=16
3. Interrupt controller. Email Resource http://sdelaycomputersam.ru/Controller_irq.php,
4. Interrupts. Interrupt controller. Device, functions, work. Email Resource http://sdelaycomputersam.ru/Controller_irq.php
5. Structure and initialization of the Intel 8259A interrupt controller E-resource https://dev64.wordpress.com/2012/05/30/8259-programming/

It's good when, after assembly or planned modernization, the computer starts up the first time and works stably and without glitches. It is much worse if unexpected problems arise - spontaneous reboots and freezes, program crashes, inoperability or "invisibility" of devices, etc. The first reason that usually comes to mind in this case is an interrupt conflict. Do we know well the nature of this phenomenon, are we sufficiently prepared to fight it?

What is IRQ
Interrupts are the basic mechanism of the system's reaction to emerging events. Hardware interrupts, usually called IRQs (Interrupt ReQuest), are physical signals, with the help of which the device controller informs the processor about the need to process some request. Conventionally, the interrupt handling scheme looks like this:
1) the processor receives an interrupt signal and its number;
2) a special table is used to find the address of the program responsible for processing the interrupt with the given number - the interrupt handler;
3) the processor suspends current job and switches to the execution of the handler (in the general case, this is some kind of driver);
4) the driver gains access to the device and checks the cause of the interrupt;
5) the requested actions are launched - initialization, device configuration, data exchange, etc.
6) the driver exits and the processor returns to the interrupted task.
Obviously, for the interrupt mechanism to work correctly, two conditions must be met: firstly, the request signal must reach the processor and, secondly, the handler driver must correctly respond to this signal. In the event of a conflict, the second condition is not met: the interrupt signal arrives, but the reaction to it turns out to be incorrect, as a result of which we have (at best) an inoperative device.

Conflict
We can say that a conflict is a situation in which several objects simultaneously try to access a resource that is intended for only one of them. An interrupt conflict occurs when multiple devices use the same interrupt line to send a request signal and there is no mechanism to handle the concurrent requests. If the driver, receiving control, does not work with the device that sent the request, then either a failure occurs, or one of the devices simply does not work.
The question arises: can several devices use the same interrupt line, or is it impossible in principle? After all, if the driver is able to determine from whom exactly the request came, then it will respond to signals from only "its" device, ignoring all the others. But this must be agreed in advance in some way, otherwise the conflict is inevitable.
The local PCI bus was designed with interrupt sharing in mind. Each PCI device must work correctly on the same interrupt line with other PCI devices. This is done in the following way: the fact of the presence of a signal on the interrupt line is determined not by the edge, i.e. a change in the voltage level, but by the very fact of the presence of a certain voltage. Several devices can change the voltage in the line at once, becoming, as it were, in a queue for service.
Thus, sharing the same IRQ among multiple PCI devices is not a conflict by definition. However, sometimes problems do arise. First, not all PCI devices work correctly on the same interrupt line with others. Secondly, sometimes drivers have errors due to which they cannot correctly determine the signal source, interfering with other drivers. Thirdly, not all devices operate on the PCI bus; for example, ISA devices, which include, for example, COM / LPT port controllers, cannot share interrupts with others. To be clear about how you can avoid or resolve conflicts, you need to understand how IRQs are managed.

Organization of hardware interrupts in a personal computer
As you know, personal computers started with the IBM PC. Its architecture included eight hardware interrupt (IRQ) lines, which were controlled by a special controller. Each of them was assigned a number that determined the priority of the interrupt and the address of its handler (the so-called interrupt vector). The new architecture, the IBM PC AT, provided eight more interrupt lines, for which a second controller was used, connected to one of the interrupt lines of the first controller. Unfortunately, this architecture was the last after IBM lost the ability to manage the development of the platform it created, so all modern computers still have only sixteen interrupts, one of which is used by the second controller.
The IBM PC AT computer had only one bus over which devices could communicate with the processor and memory - ISA. Most of the interrupt lines were assigned to standard ISA devices, the rest were reserved for the future. When this future came, it became clear that the new universal bus PCI got only four free interrupts. Therefore, a clever mechanism for sharing interrupts (IRQ Sharing) and dynamic redefinition of numbers (IRQ Steering or Mapping) was invented.
The essence of the PCI device interrupt control mechanism is as follows. In general, there are four physical PCI interrupt lines called PIRQ0, PIRQ1, PIRQ2, and PIRQ3. They are connected to the interrupt controller. Each PCI device, for its part, seems to have four connectors, called INT A, INT B, INT C and INT D. You can connect the lines to the connectors in any order. For example, for the first PCI slot, you can make the following wiring: PIRQ0 - INT A, PIRQ1 - INT B, PIRQ2 - INT C, PIRQ3 - INT D. And for the second - in a different way: PIRQ0 - INT B, PIRQ1 - INT C, PIRQ2 - INT D, PIRQ3 - INT A. Usually the device requires only one interrupt line connected to INT A. When installed in the first slot, the device uses the PIRQ0 line, and in the second slot, the PIRQ1 line will be on the same pin. Thus, devices in different slots will use different physical interrupt lines. A hardware conflict between them will be eliminated.
The AGP bus, being in fact a specialized PCI modification, also uses one of the PIRQ lines - usually PIRQ0.
For modern systems, four lines are not enough, so new chipsets often use eight PIRQ lines, which are connected in the same way in different combinations to PCI slots and devices built into the board.
The PIRQ lines are connected to the interrupt controller. They, like other lines, are assigned logical IRQ numbers. If there are several devices on the same physical line (and this is permissible), then they will all have the same IRQ number. If devices are on different physical lines, they can still receive the same IRQ numbers. Normal drivers will allow them to run freely without sacrificing performance, since the PCI bus can still only be captured by one device. The main thing is to recognize from which device the signal came.
PIRQ line numbers are assigned automatically thanks to the notorious Plug & Play mechanism. But there are also Plug & Play ISA devices. They also have the ability to automatically obtain an IRQ number. But their interrupt line belongs to them exclusively, and if one of the PIRQ lines gets the same number, an insoluble conflict will arise.
So we figured out that PCI devices should be free of IRQ conflict issues. If they, of course, work correctly, and this is not always the case. In addition, drivers must support an interrupt sharing mechanism. ISA devices do not know how to share interrupt lines and therefore are conflict provocateurs. Consequently, the problem of eliminating conflicts is reduced to the correct allocation of numbers (the source of the problems is ISA devices and "crooked" drivers) or to separation along different physical lines ("crooked" PCI controllers).
Let's look at how numbers are allocated in the system and how we can influence this process.

Interrupt map
As I said, most of the IRQ numbers are already taken by standard devices, or rather, assigned to their interrupt lines. Let's go through the order:
0 - system timer (the number is always busy);
1 - keypad (the number is always busy);
2 - second interrupt controller (always busy);
3 - COM2 port (can be disabled, and the number can be released);
4 - COM1 port (can be disabled, and the number can be released);
5 - LPT2 port (usually the number is free);
6 - floppy disk controller (can be disabled and number released);
7 - LPT1 port (if not in EPP or ECP mode, then the number is free);
8 - real time clock (always busy);
9 - free;
10 - free;
11 - free;
12 - PS / 2 mouse (can be free if there is no such mouse);
13 - coprocessor (always busy);
14 and 15 - controller hard drives(can be disabled, and the number is vacated).
In a typical system, numbers 5, 7, 9-11 are available, that is, five out of fifteen. In addition, you can safely disable COM2 and LPT1 ports, increasing the number of free numbers to seven. Free does not mean that they are not busy, it is just that free shuffling is possible between them.
Any system has three standard PCI devices - ACPI, USB controllers, and a video card, each of which will take one number. A complex device (for example, sound card) may require multiple lines - INT A, INT B, etc. for their components, which will not conflict with each other (after all, different physical lines), but with other devices - easily.
You can find out how the interrupt numbers are currently allocated in several ways. At the very beginning of the computer boot, a text configuration table appears. Right after it there is a list of PCI devices with the assigned IRQ number (see screenshot). Another way works on Windows 9x. There is a "System" icon in the control panel, and the "Devices" tab in the called applet. We select the properties of the "Computer" device, and all devices will be listed there, indicating their IRQ (see screenshot).
In Windows 2000, we do not have access to interrupt management, so to view the IRQ list, we need to use the standard information utility (Control Panel / Administrative Tools / Computer Management / System Information / Hardware Resources).

BIOS IRQ allocation
In the system, IRQ numbers are allocated between physical lines twice. The first time this is done by the system BIOS at system boot. Each Plug & Play device (all PCI, modern ISA, integrated devices), or rather its interrupt line, is assigned one out of ten possible numbers. If there are not enough numbers, several lines get one common one. If these are PIRQ lines, then it's okay - in the presence of normal drivers and support from the operating system (see below for more on this), everything will work. And if several ISA devices or PCI and ISA devices get the same number, then the conflict is simply inevitable, and then it is necessary to intervene in the distribution process.
First of all, you need to disable all unused ISA devices (in systems without ISA slots, they are also present) - ports COM1, COM2 and a floppy drive. You can also disable the EPP and ECP modes of the LPT port, then the IRQ7 interrupt will become available.
V BIOS Setup we need the "PCI / PNP Configuration" section. There are two basic ways to influence the allocation of IRQ numbers: block a specific number and directly assign a PIRQ line number.
The first method is available for all BIOS: find the list of items "IRQ x used by:" (in new BIOS hidden in the "IRQ Resources" submenu). Those interrupts that should be assigned exclusively to ISA devices should be set to "Legacy ISA". Thus, when assigning numbers to PCI devices, these interrupts will be skipped. This should be done if an ISA device persists in one interrupt with a PCI device, because of which both do not work. Then we find the number of this IRQ and block it in BIOS Setup. PCI device goes to new number IRQ, but the ISA device remains. Conflict resolved.
A second, more convenient way to control IRQ numbers is direct assignment. In the same BIOS Setup submenu, there may be items of the form "Slot X use IRQ" (other names: "PIRQx use IRQ", "PCI Slot x priority", "INT Pin x IRQ").
With their help, each of the four PIRQ lines can be assigned a specific number. By the way, in the new AwardBIOS 6.00 you can see exactly which devices (including built-in ones) use this or that line. Just look at right side BIOS Setup screen: the photo shows how I hovered the cursor over the item "Slot 1/5 use IRQ no.", and the inscription "Display Contr." appeared on the right. That is, the first PIRQ line is used by the video card. If I now put any specific number instead of "Auto", the video card will be switched to this interrupt.

Allocation of IRQ numbers Windows tools
The second time the interrupt numbers are allocated operating system... As shown by my experiments, Windows "98 begins to interfere with the actions performed by the BIOS" ohm only in extreme cases. If you have a normal BIOS, the techniques described here are not needed.
It should be noted that the correct operation of the IRQ sharing and dynamic allocation mechanisms requires Windows to recognize the chipset. motherboard and downloaded IRQ Miniport. The more recent version Windows has, the more chipsets support its own miniport (PCIIMP.PCI). However, it's always best to play it safe and install the most recent chipset drivers.
In Windows 98, the IRQ allocation system is controlled by the standard device manager. In the list system devices you need to find the PCI bus. There is a special tab in its properties (see screenshot). If everything is configured correctly, the miniport will be mentioned there ("successfully loaded"), and the control PCI bus(Steering) will be enabled. Thus, Windows "98 has a means to control the distribution of interrupt numbers between physical lines. But since the BIOS also copes well with this, this mechanism is not involved.
But sometimes it is simply necessary. As I said before, PCI devices should not conflict if they use the same logical interrupt. Another thing is ISA devices, which also include COM and LPT ports. If the device is non-Plug & Play, the BIOS may not notice it by giving the interrupt it is busy with to the PCI device. Then you need to reserve the interrupt. This is done in the dispatcher Windows devices"98: select the" Computer "device, call its properties, switch to the second tab. Then everything is clear.
In addition to redundancy, you can directly set the interrupt number for the device. To do this, you need to find the "Resources" tab in its properties, disable automatic tuning and try to change the assigned interrupt number.
Unfortunately, this does not always work.
Windows 2000 is a special system. If you have modern computer then it probably supports the ACPI configuration interface. In this case, Windows 2000 will ignore the BIOS actions altogether and "hang" all PCI devices on one logical interrupt. In general this will work fine (when there is no ISA), but sometimes problems do happen. To be able to change interrupt numbers, either change the HAL kernel or reinstall Windows 2000 with ACPI disabled in the BIOS. Replacing the kernel is done as follows: in the device manager, select "Computer" / "Computer with ACPI", change the driver to " Standard computer", reboot. If that doesn't work, you'll have to reinstall Windows 2000 again.
I hope the above information will help you in your fight against hardware glitches. And remember: most of the problems that arise are related to low level computer literacy the host of the computer. Therefore, you must always strive for self-education, then there will be fewer problems, and those that do arise will not seem insoluble.

Probably the most common interrupt conflict (IRQ) is associated with the integrated serial port COM2 found in modern motherboards, and an internal modem (meaning a full-fledged internal PC modem, not a software modem, also called WinModem). The fact is that a full-fledged internal modem already has support for a certain port; by default, this port is assigned to COM2, with the system also usually enabling the second serial port. Thus, the system has two identical ports using the same resources (interrupts and I / O port addresses).

The solution to this problem is quite simple: enter the system BIOS Setup and disable the built-in COM2 port. In addition, you might consider disabling the COM1 port, which is also rarely used. Disabling unused COMx ports is one of the better ways release interrupts (IRQs) for other devices.

Another common conflict also involves serial ports. In the standard interrupt mapping table, you may have noticed that IRQ3 is assigned to COM2 and IRQ4 is assigned to COM1. The problem arises when additional COM3 and / or COM4 ports are added to the system and free interrupts are not manually assigned to them (by default they use the same IRQ3 and IRQ4).

Additional complications are introduced by the fact that some port cards do not allow the selection of interrupts other than IRQ3 and IRQ4. As a result, assigning IRQ3 to COM4 and IRQ4 to COM3 leads to a conflict with COM1 and COM2, which also use these interrupts: two ports cannot simultaneously use the same interrupt control channel. While working in DOS, this was allowed, since only one task could be performed in it at a time, but in Windows and OS / 2 this is completely impossible. In order to be able to use more than two parallel COM ports in a computer, a multiport board is required, which, in addition to interrupts numbered 3 and 4, allows the use of additional interrupts. Sharing interrupts is, in principle, acceptable for devices that normally do not work simultaneously (or continuously). Ports do not fall into this device category. It is possible to use the interrupt for the scanner and the modem together, however, in this case, if they are used simultaneously, a conflict will arise. Fortunately, most devices that previously used ports (such as mice, label printers, and external modems) now connect to USB ports, so there are problems with the need to support multiple ports. modern users computers should not appear.

If you still need to use multiple serial ports, the best solution will be the purchase of a multiport board that either provides the ability to set non-conflicting interrupts, or contains its own processor that allows one system interrupt to be distributed among several ports. Some older multiport cards had an ISA interface, but today they have been replaced by PCI cards, which also offer performance advantages.

If some device mentioned in the table is missing (for example, the built-in mouse port (IRQ12) or the second parallel port (IRQ5)), their interrupts can be considered available. For example, the second parallel port is extremely rare, so the IRQ5 interrupt assigned to it is most often used for the sound adapter card. Likewise, the IRQ15 interrupt is used for the secondary IDE controller. If there are no disk devices connected to the secondary IDE channel in the system, you can disable this controller in the BIOS, thereby freeing up another interrupt for other devices.

It should be noted that the easiest way to check your interrupt settings is in Windows Device Manager. On Windows 95b there is the HWDIAG program, and on Windows 98 and above later versions- Console System Information. These utilities allow you to get a detailed report on the use of resources in the system, as well as installed drivers devices and Windows registry entries for each device. V Windows systems For XP and Vista, the system information is provided by the Msinfo32 program.

To ensure the highest possible number of shared interrupts in a modern system without ISA connectors, use the following steps in the system BIOS.

1. Disable any unused ports in the system BIOS. For example, if instead of serial and parallel ports are used USB ports, disable them. As a result, up to three interrupts can be released.
2. Specify the IRQ interrupt released in step 1 in the list of available interrupts for PCI / PnP devices. Depending on the BIOS version the corresponding parameters are available in the PnP / PCI Resource Exclusion or PnP / PCI Configuration section.
3. Activate the Reset Configuration Data option to clear the IRQ routing tables in CMOS memory.
4. Save changes and exit BIOS setup program.

It's good when, after assembly or planned modernization, the computer starts up the first time and works stably and without glitches. It is much worse if unexpected problems arise - spontaneous reboots and freezes, program crashes, inoperability or "invisibility" of devices, etc. The first reason that usually comes to mind in this case is an interrupt conflict. Do we know well the nature of this phenomenon, are we sufficiently prepared to fight it?

What is IRQ

Interrupts are the basic mechanism of the system's reaction to emerging events. Hardware interrupts, usually called IRQs (Interrupt ReQuest), are physical signals used by the device controller to inform the processor to process some request. Conventionally, the interrupt handling scheme looks like this:
1) the processor receives an interrupt signal and its number;
2) a special table is used to find the address of the program responsible for processing the interrupt with the given number - the interrupt handler;
3) the processor suspends the current work and switches to the execution of the handler (in the general case, this is some kind of driver);
4) the driver gains access to the device and checks the cause of the interrupt;
5) the requested actions are launched - initialization, device configuration, data exchange, etc.
6) the driver exits and the processor returns to the interrupted task.
Obviously, for the correct operation of the interrupt mechanism, two conditions must be met: firstly, the request signal must reach the processor and, secondly, the handler driver must correctly respond to this signal. In the event of a conflict, the second condition is not met: the interrupt signal arrives, but the reaction to it turns out to be incorrect, as a result of which we have (at best) an inoperative device.

Conflict

We can say that a conflict is a situation in which several objects simultaneously try to access a resource that is intended for only one of them. An interrupt contention occurs when multiple devices use the same interrupt line to send a request signal and there is no mechanism to handle concurrent requests. If the driver, receiving control, does not work with the device that sent the request, then either a failure occurs, or one of the devices simply does not work.
The question arises: can several devices use the same interrupt line, or is it impossible in principle? After all, if the driver is able to determine from whom exactly the request came, then it will respond to signals from only "its" device, ignoring all the others. But this must be agreed in advance in some way, otherwise the conflict is inevitable.
The local PCI bus was designed with interrupt sharing in mind. Each PCI device must work correctly on the same interrupt line with other PCI devices. This is done in the following way: the fact of the presence of a signal on the interrupt line is determined not by the edge, i.e. a change in the voltage level, but by the very fact of the presence of a certain voltage. Several devices can change the voltage in the line at once, becoming, as it were, in a queue for service.
Thus, sharing the same IRQ among multiple PCI devices is not a conflict by definition. However, sometimes problems do arise. First, not all PCI devices work correctly on the same interrupt line with others. Secondly, sometimes drivers have errors due to which they cannot correctly determine the signal source, interfering with other drivers. Thirdly, not all devices operate on the PCI bus; for example, ISA devices, which include, for example, COM / LPT port controllers, cannot share interrupts with others. To be clear about how you can avoid or resolve conflicts, you need to understand how IRQs are managed.

Organization of hardware interrupts in a personal computer

As you know, personal computers began with the IBM PC. Its architecture included eight hardware interrupt (IRQ) lines, which were controlled by a special controller. Each of them was assigned a number that determined the priority of the interrupt and the address of its handler (the so-called interrupt vector). The new architecture, the IBM PC AT, provided eight more interrupt lines, for which a second controller was used, connected to one of the interrupt lines of the first controller. Unfortunately, this architecture was the last after IBM lost the ability to manage the development of the platform it created, so all modern computers still have only sixteen interrupts, one of which is used by the second controller.
The IBM PC AT computer had only one bus over which devices could communicate with the processor and memory - ISA. Most of the interrupt lines were assigned to standard ISA devices, the rest were reserved for the future. When that future came, it turned out that the new universal PCI bus got only four free interrupts. Therefore, a clever mechanism for sharing interrupts (IRQ Sharing) and dynamic redefinition of numbers (IRQ Steering or Mapping) was invented.
The essence of the PCI device interrupt control mechanism is as follows. In general, there are four physical PCI interrupt lines called PIRQ0, PIRQ1, PIRQ2, and PIRQ3. They are connected to the interrupt controller. Each PCI device, for its part, seems to have four connectors, called INT A, INT B, INT C and INT D. You can connect the lines to the connectors in any order. For example, for the first PCI slot, you can make the following wiring: PIRQ0 - INT A, PIRQ1 - INT B, PIRQ2 - INT C, PIRQ3 - INT D. And for the second - in a different way: PIRQ0 - INT B, PIRQ1 - INT C, PIRQ2 - INT D, PIRQ3 - INT A. Usually the device requires only one interrupt line connected to INT A. When installed in the first slot, the device uses the PIRQ0 line, and in the second slot, the PIRQ1 line will be on the same pin. Thus, devices in different slots will use different physical interrupt lines. A hardware conflict between them will be eliminated.
The AGP bus, being in fact a specialized PCI modification, also uses one of the PIRQ lines - usually PIRQ0.
For modern systems, four lines are not enough, so new chipsets often use eight PIRQ lines, which are connected in the same way in different combinations to PCI slots and onboard devices.
PIRQ lines are connected to the interrupt controller. They, like other lines, are assigned logical IRQ numbers. If there are several devices on the same physical line (and this is permissible), then they will all have the same IRQ number. If devices are on different physical lines, they can still receive the same IRQ numbers. Normal drivers will allow them to run freely without sacrificing performance, since the PCI bus can still only be captured by one device. The main thing is to recognize from which device the signal came.
PIRQ line numbers are assigned automatically thanks to the notorious Plug & Play mechanism. But there are also Plug & Play ISA devices. They also have the ability to automatically obtain an IRQ number. But their interrupt line belongs to them exclusively, and if one of the PIRQ lines gets the same number, an insoluble conflict will arise.
So we figured out that PCI devices should be free of IRQ conflict issues. If they, of course, work correctly, and this is not always the case. In addition, drivers must support interrupt sharing. ISA devices do not know how to share interrupt lines and therefore are conflict provocateurs. Therefore, the problem of eliminating conflicts comes down to the correct allocation of numbers (the source of the problems is ISA devices and "crooked" drivers) or to the separation along different physical lines ("crooked" PCI controllers).
Let's look at how numbers are allocated in the system and how we can influence this process.

Interrupt map

As I said, most of the IRQ numbers are already occupied by standard devices, or rather, assigned to their interrupt lines. Let's go through the order:
0 - system timer (the number is always busy);
1 - keypad (the number is always busy);
2 - second interrupt controller (always busy);
3 - COM2 port (can be disabled, and the number can be released);
4 - COM1 port (can be disabled, and the number can be released);
5 - LPT2 port (usually the number is free);
6 - floppy disk controller (can be disabled and number released);
7 - LPT1 port (if not in EPP or ECP mode, then the number is free);
8 - real time clock (always busy);
9 - free;
10 - free;
11 - free;
12 - PS / 2 mouse (can be free if there is no such mouse);
13 - coprocessor (always busy);
14 and 15 - hard disk controller (can be disabled and number released).
In a typical system, numbers 5, 7, 9-11 are available, that is, five out of fifteen. In addition, you can safely disable COM2 and LPT1 ports, increasing the number of free numbers to seven. Free does not mean that they are not busy, it is just that free shuffling is possible between them.
Any system has three standard PCI devices - ACPI, USB controllers, and a video card, each of which will take one number. A complex device (for example, a sound card) may require several lines - INT A, INT B, etc. for their components, which will not conflict with each other (after all, different physical lines), but with other devices - easily.
You can find out how the interrupt numbers are currently allocated in several ways. At the very beginning of the computer boot, a text configuration table appears. Right after it there is a list of PCI devices with the assigned IRQ number (see screenshot). Another way works on Windows 9x. There is a "System" icon in the control panel, and the "Devices" tab in the called applet. We select the properties of the "Computer" device, and all devices will be listed there, indicating their IRQ (see screenshot).
In Windows 2000, we do not have access to interrupt management, so to view the IRQ list, we need to use the standard information utility (Control Panel / Administrative Tools / Computer Management / System Information / Hardware Resources).

BIOS IRQ allocation

In the system, IRQ numbers are allocated between physical lines twice. The first time this is done by the system BIOS at system boot. Each Plug & Play device (all PCI, modern ISA, integrated devices), or rather its interrupt line, is assigned one out of ten possible numbers. If there are not enough numbers, several lines get one common one. If these are PIRQ lines, then it's okay - in the presence of normal drivers and support from the operating system (see below for more on this), everything will work. And if several ISA devices or PCI and ISA devices get the same number, then the conflict is simply inevitable, and then it is necessary to intervene in the distribution process.
First of all, you need to disable all unused ISA devices (in systems without ISA slots, they are also present) - ports COM1, COM2 and a floppy drive. You can also disable the EPP and ECP modes of the LPT port, then the IRQ7 interrupt will become available.
In BIOS Setup, we need the "PCI / PNP Configuration" section. There are two basic ways to influence the allocation of IRQ numbers: block a specific number and directly assign a PIRQ line number.
The first method is available for all BIOSes: find the list of items "IRQ x used by:" (in new BIOS it is hidden in the "IRQ Resources" submenu). Those interrupts that should be assigned exclusively to ISA devices should be set to "Legacy ISA". Thus, when assigning numbers to PCI devices, these interrupts will be skipped. This should be done if an ISA device persists in one interrupt with a PCI device, because of which both do not work. Then we find the number of this IRQ and block it in BIOS Setup. The PCI device moves to the new IRQ number, but the ISA device remains. Conflict resolved.
A second, more convenient way to control IRQ numbers is direct assignment. In the same BIOS Setup submenu, there may be items of the form "Slot X use IRQ" (other names: "PIRQx use IRQ", "PCI Slot x priority", "INT Pin x IRQ").
With their help, each of the four PIRQ lines can be assigned a specific number. By the way, in the new AwardBIOS 6.00 you can see exactly which devices (including built-in ones) use this or that line. Just take a look at the right side of the BIOS Setup screen: the photo shows how I hovered the cursor over the item "Slot 1/5 use IRQ no.", And the words "Display Contr." Appeared on the right. That is, the first PIRQ line is used by the video card. If I now put any specific number instead of "Auto", the video card will be switched to this interrupt.

Allocating IRQs Using Windows

The second time the interrupt numbers are allocated by the operating system. As shown by my experiments, Windows "98 begins to interfere with the actions performed by the BIOS" ohm only in extreme cases. If you have a normal BIOS, the techniques described here are not needed.
It should be noted that for the IRQ sharing and dynamic allocation mechanisms to work properly, Windows must recognize the motherboard chipset and load the IRQ Miniport. The more recent version Windows has, the more chipsets support its own miniport (PCIIMP.PCI). However, it's always best to play it safe and install the most recent chipset drivers.
In Windows 98, the IRQ allocation system is controlled using the standard device manager. Find the PCI bus in the list of system devices. There is a special tab in its properties (see screenshot). If everything is configured correctly, a miniport will be mentioned there ("successfully loaded"), and PCI bus management (Steering) will be enabled. Thus, Windows "98 has the means to control the distribution of interrupt numbers between physical lines. But since the BIOS also copes well with this, this mechanism is not involved.
But sometimes it is simply necessary. As I said before, PCI devices should not conflict if they use the same logical interrupt. Another thing is ISA devices, which also include COM and LPT ports. If the device is non-Plug & Play, the BIOS may not notice it by giving the interrupt it is busy with to the PCI device. Then you need to reserve the interrupt. This is done in the Windows 98 Device Manager: select the Computer device, call its properties, switch to the second tab.
In addition to redundancy, you can directly set the interrupt number for the device. To do this, you need to find the "Resources" tab in its properties, disable automatic configuration and try to change the assigned interrupt number.
Unfortunately, this does not always work.
Windows 2000 is a special system. If you have a modern computer, then it probably supports the ACPI configuration interface. In this case, Windows 2000 will ignore the BIOS actions altogether and "hang" all PCI devices on one logical interrupt. In general this will work fine (when there is no ISA), but sometimes problems do happen. To be able to change interrupt numbers, you need to either change the HAL kernel, or reinstall Windows 2000 with ACPI disabled in the BIOS. Replacing the kernel is done as follows: in the device manager, select "Computer" / "Computer with ACPI", change the driver to "Standard computer", reboot. If this does not help, you will have to reinstall Windows 2000 again.
I hope the above information will help you in your fight against hardware glitches. And remember: most of the problems that arise are associated with the low level of computer literacy of the computer owner. Therefore, you must always strive for self-education, then there will be fewer problems, and those that do arise will not seem insoluble.